1. Field of the Invention
The present invention relates to a microprocessor boot-up controller and a nonvolatile memory controller. It also relates to an information processing system using a microprocessor boot-up controller and a nonvolatile memory.
2. Description of the Related Art
A system in which a nonvolatile memory (e.g., NAND flash memory) is used as a boot read-only memory (boot ROM) permits a host central processing unit (CPU) to access a SRAM as a boot ROM after transfer of NAND read data to the static random access memory (SRAM).
On the other hand, an access to SRAM from the host CPU must be disabled by bringing the host CPU into a wait state until the SRAM enters a read ready state after loading data to the SRAM from the NAND nonvolatile memory. The relaxed art includes a mechanism for generating and providing a power-on reset signal to a boot controller and a CPU, and canceling the power-on reset signal to the CPU when a SRAM in the boot controller enters an access ready state.
A boot system using NAND flash memory and a booting method for the same have been disclosed (e.g., Japanese Patent Application Laid-Open No. 2003-271391). In addition, a nonvolatile semiconductor memory device, which writes system boot data in an arbitrary address of a NAND flash memory used as file memory, for example, has also been disclosed (e.g., Japanese Patent Application Laid-Open No. 2003-162453). Furthermore, boot codes and a NAND flash memory have been disclosed (e.g., Japanese Patent Application Laid-Open No. 2003-114826 and U.S. Pat. No. 5,519,843). In addition, a configuration of a multi-valued NAND cell has been disclosed (e.g., Japanese Patent Application Laid-Open No. 2002-313089).
When using multi-valued NAND nonvolatile memory as the boot ROM, there is a problem that the multi-valued NAND nonvolatile memory tends to cause a change in data due to a slight threshold voltage variation, which may be due to age deterioration in a data holding circuit, more easily than a two-valued NAND nonvolatile memory, and thus is less reliable. Therefore, it is difficult to provide a nearly error-free highly reliable boot system.
On the other hand, a problem of generating and providing a power-on reset signal to a boot controller and a CPU, and canceling the power-on reset signal to the CPU when a SRAM in the boot controller enters an access ready state is complexity of a power-on reset circuit. The availability of the SRAM varies due to capacity of the program to be loaded in the SRAM, retry due to an erroneous NAND read-in data, error correction or the like. Therefore, a CPU reset must always be cancelled in a worst-case timing. Accordingly, CPU reset cannot be cancelled in the shortest time in sync with the time when the SRAM becomes ready, creating a problem in that average system boot-up time cannot be reduced.